Referring now to FIG. 1, an exemplary magnetic storage system 100, such as a hard disk drive, is shown. A buffer 102 stores data that is associated with control of the hard disk drive. The buffer 102 may employ SDRAM or other types of low latency memory. A processor 104 performs processing that is related to the operation of the hard disk drive. A hard disk controller (HDC) 106 communicates with the buffer 102, the processor 104, a host 108 via an I/O channel 110, a spindle/voice coil motor (VCM) driver 112, and a read/write channel circuit 114.
One or more hard drive platters 116 include a magnetic recording media that stores magnetic fields. The platters 116 are rotated by a spindle motor that is shown schematically at 118. Generally, the spindle motor 118 rotates the hard drive platters 116 at a fixed speed during read/write operations. One or more read/write arm(s) 120 move relative to the platters 116 to read and/or write data to/from the hard drive platters 116. The spindle/VCM driver 112 controls the spindle motor 118, which rotates the platters 116. The spindle/VCM driver 112 also generates control signals that position the read/write arm 120, for example using a voice coil actuator, a stepper motor, or any other suitable actuator.
A read/write device 122 is located near a distal end of the read/write arm 120. The read/write device 122 includes a write element such as an inductor that generates a magnetic field. The read/write device 122 also includes a read element (such as a magneto-resistive (MR) sensor) that senses the magnetic fields on the platter 116. A preamplifier (preamp) circuit 124 amplifies analog read/write signals received from the read/write device 122. When reading data, the preamp circuit 124 amplifies low level signals from the read element and outputs the amplified signal to the read/write channel circuit 114. While writing data, a write current that flows through the write element of the read/write channel circuit 114 is switched to produce a magnetic field having a positive or negative polarity. The positive or negative polarity is stored by the hard drive platter 116 to represent data.
During a write operation, the read/write channel circuit 114 encodes the data to be written onto the storage medium. The read/write channel circuit 114 processes the signal for reliability and may include, for example, error checking and correcting (ECC) coding and run length limited (RLL) coding. During read operations, the read/write channel circuit 114 converts an analog output from the medium to a digital signal. The converted signal is then detected and decoded by known techniques to recover the data written on the hard disk drive.
In longitudinal recording, the read/write device 122 records each bit by magnetizing a portion of the magnetic recording media in the direction that the magnetic recording media rotates. In perpendicular recording, the transducer records data by magnetizing a portion of the magnetic recording media in a direction perpendicular to the rotation of the magnetic recording media. Perpendicular recording channels achieve a higher signal error rate (SER) and thus a lower Bit Error Rate (BER) using a target channel response with a DC term. In longitudinal recording channels, the optimum channel response is DC free. In other words, the channel response has a (1-D) factor.
Conventional channel technologies using AC coupling have been built and optimized for longitudinal recording. DC-coupled channels are difficult to implement. In addition, the performance of longitudinal recording channels are relatively insensitive to a low-to-moderate high-pass corner coupling frequency. Therefore, conventional channels are designed to have AC filters. In FIG. 1, the read/write channel 114 and the preamp 124 are shown to include AC filters 117 and 127 respectively. For perpendicular recording, however, AC coupling causes baseline-wander. The read/write channel for perpendicular recording typically implements a baseline tracking circuit to remove the baseline wander.
Limited bandwidth of the baseline correction loop has placed a practical limitation on the maximum allowed high pass corner of the AC coupling paths. Conventional baseline correction loops typically can handle an AC coupling corner frequency that is about 0.1% to 0.2% of the channel data rate without causing significant BER degradation in the channel.